In an information processing system which employs a central system memory for storing information units, such as operands and instructions, an important consideration is the coupling of the system memory to a central system bus. In order to achieve and maintain a desired system bus bandwidth it is important that data read and write operations which access the system memory occur in a rapid manner. It is also important, for those systems which employ one or more system bus units, or bus connections, that substantially simultaneous multiple read and write accesses which target a given memory location occur such that the read and write operations are correctly sequenced. That is, if one bus connection desires to read a given memory location while another bus connection desires to write the same location the sequencing of these two operations must be such that the data read reflects the current state of the data.
Related to both of the above considerations is an underlying goal of providing the data to a requesting bus connection without the introduction of errors resulting from hard or soft memory storage device errors. In this regard it has been known to provide additional memory storage devices to store error correction and detection syndrome bits which advantageously correct single bit errors and detect multiple bit errors occurring in data words stored within the system memory. It has also been known to provide, for memory systems which employ dynamic random access memories (DRAM), error "sniffing" and "scrubbing" techniques which detect and correct errors during the required memory refresh cycles.
It can be realized however that error detection and correction techniques require some finite amount of time to accomplish. During a read of the system memory this additional time is typically incurred for each memory access, resulting in a longer access cycle and a consequent reduction in the overall bandwidth of the system bus.